1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing it and, more particularly, a transistor from which a damaged layer formed in a source/drain region during the course of processing has been removed.
2. Description of the prior art
A source/drain region of a transistor to be incorporated into DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) is formed at a very shallow depth as a semiconductor device is integrated higher.
FIG. 61 is a cross-sectional view showing an existing transistor whose source/drain region is formed from a region contains impurities in small concentrations (hereinafter referred to as a low impurity-concentration region). In the drawing, reference numeral 1 designates a silicon substrate; 2 designates an isolation field oxide formed on the surface of the silicon substrate; 3 designates a gate oxide film formed on the principal surface of the silicon substrate; 4y designates a gate electrode formed on the gate oxide film 3; and 5 designates a source/drain region which is a low impurity-concentration region formed on the surface of the silicon substrate 1 while a channel region (not shown) is sandwiched between the surface of the substrate and the gate electrode 4y to be used as a mask by ion implantation. Side wall insulating material 6y is formed on each side of the gate electrode by RIE (Reactive Ion Etching). As a result, a damaged layer 7 is formed on the source/drain region 5 (which will be hereinafter often referred to as a low impurity-concentration region) by RIE with the exception of the area immediately below the side wall insulating material 6.
With the foregoing construction of the existing semiconductor device, when the transistor is turned on by application of an electric potential to the gate electrode, an electric current flows to the source/drain region. In contrast, the transistor is turned off in the absence of the electrical potential applied to the gate electrode, so that an electric current does not flow to the source/drain region.
To ensure high-speed and stable operation of the transistor incorporated into DRAM or SRAM, a region which is formed from n-type or p-type impurities on the surface of the silicon substrate is generally required to have superior conductivity, and superior junction characteristics must be accomplished between the impurity region and the silicon substrate having the conductivity opposite to that of the impurity region. However, the damaged layer that contains crystal imperfections or a deteriorated layer caused by RIE impairs the characteristics of the junction between the impurity region and the silicon substrate which serves as an insulator when reverse bias is applied.
FIGS. 62A and 62B are schematic representations showing a mechanism of how the damaged layer 7 causes a leakage current in the junction. In FIGS. 62A and 62B, the elements assigned the same reference numerals as those used in FIG. 61 denote the corresponding elements which are assigned the same reference numerals in FIG. 61. FIG. 62A is a cross-sectional view showing the left half of the existing transistor in FIG. 61 whose the source/drain region is formed from a low impurity-concentration region. In this drawing, the silicon substrate is of a p-type, and the source/drain region is of an n-type. FIG. 62B is a schematic diagram of an energy band taken across line I--I in FIG. 61A. In this drawing, x denotes crystal imperfections or deteriorated areas. As can be seen from this drawing, a depletion layer in which electrons or positive holes are not present exists between the p-type silicon substrate and the n-type source/drain region having a low concentration of impurities. By virtue of this depletion layer, in a normal state, electric conduction does not occur in the junction between the source/drain region and the silicon substrate, thereby preventing leakage current from arising in the junction. However, when the transistor is in operation or the capacitor of the DRAM memory cell stores electric charges, the depletion layer is increased so as to include crystal imperfections or deteriorated areas designated by x. As a result, the crystal imperfections or deteriorated areas cause leakage current in the junction between the source/drain region 5 and the silicon substrate 1.
As described above, the damaged layer 7 impairs the characteristics of the junction between the silicon substrate 1 and the source/drain region 5 which acts as an insulator when reverse bias is applied. In a MOS (Metal Oxide Semiconductor) device, the leakage current occurred in the junction increases, which in turn increases power consumption. Particularly, in a DRAM memory cell, the electric charges stored in the capacitor are discharged to the outside, thereby impairing the refreshing characteristics of the DRAM memory cell. In short, the damaged layer 7 causes an increase in the power consumption of the semiconductor device or instable operations of the same.
There is one method of solving the previously-described problems; namely, a method of removing the damaged layer 7 after the side wall insulating material 6y has been formed. FIG. 63 is a cross-sectional view similar to FIG. 61, but a recess 8 is formed by etching away the damaged layer 7 formed on the source/drain region 5 with the exception of the area immediately below the side wall insulating material 6y. In FIG. 63, the elements assigned the same reference numerals as those used in FIG. 61 denote the corresponding elements which are assigned the same reference numerals in FIG. 61. As a result of removal of the damaged layer 7 from the source/drain region 5, the superior characteristics of the junction between the silicon substrate 1 and the source/drain region 5 are obtained.
Explanations will be given of a LDD (Lightly Doped Drain transistor which bears at first glance a resemblance to but is completely different from the transistor in FIG. 61 whose source/drain region is formed from a low impurity-concentration region; and a difference between this LDD transistor and a transistor, in accordance with the present invention, whose source/drain region is formed from a low impurity-concentration region.
FIG. 64 is a cross-sectional view of an existing LDD transistor. In FIG. 64, the elements assigned the same reference numerals as those used in FIG. 61 denote the corresponding elements which are assigned the same reference numerals in FIG. 61. In addition to the elements shown in FIG. 61, a region 9 (which contains a high concentration of impurities and is the same in conductivity type as the low impurity-concentration region 5) is formed on the surface of the substrate 1 with the exception of the area immediately below the side wall insulating material 6y by ion implantation. The low impurity-concentration region 5 constitutes the source/drain region together with the region 9 containing a high concentration of impurities (which will be hereinafter referred to as a high impurity-concentration region). (1) Since this LDD transistor has the high impurity-concentration region 9, the depletion layer is hard to extend in the direction of the principal plane including the damaged layer. (2) The LDD transistor is used in circuitry which has a comparatively large tolerance on the leakage current. For these reason(1) (2), eventually, the presence of the damaged layer does not result in a serious problem. As described above, the LDD transistor is used as a logic device or a high-performance transistor for use as a peripheral circuit of DRAM. In contrast, the transistor, in accordance with the invention, whose source/drain region is formed from a low impurity-concentration region is primarily used as a low junction-leakage transistor to be incorporated into a DRAM memory cell. The summary of the relationship between the existing LDD transistor and the transistor in accordance with the present invention is presented in Table 1.
TABLE 1 ______________________________________ LDD Transistor Transistor of the (conventional) present invention ______________________________________ Low impurity- Present Present concentration region Formation of a side Formed Formed wall Damages due to RIE Occurred Occurred High impurity- Present None concentration region Applications High-performance Low junction-leakage transistors(e.g., a transistors logic device, or a (e.g., a peripheral circuit DRAM memory cell) of DRAM) ______________________________________
As described above, the LDD transistor and the transistor of the invention completely differ from each other in terms of applications and characteristics.
In a semiconductor device having the previously-described existing transistor whose source/drain region is formed from a low impurity-concentration region, the source/drain region 5 is usually formed at a depth as shallow as 1500 .ANG. or less. If the damaged layer 7 is removed in the manner as shown in FIG. 63, the source/drain region becomes of high resistance as a result of the removal of the impurity region. Further, variations in the etch rate required for removal of the damaged layer 7 result in variations in the characteristics of the junction between the source/drain region 5 and the silicon substrate 1 or in the electrical resistance of the source/drain region 5. This, in turn, leads to a drop in the yield of the semiconductor device.